Semiconductor devices are ubiquitous. One example of a semiconductor device is a solar cell. There is a general interest in the manufacture and use of solar cells as an alternative method for energy creation. FIG. 15A illustrates one type of conventional selective emitter solar cell. This solar cell includes a silicon wafer 150a with a base region 151a of p-type conductivity, diffusion regions 162 of p+-type, a low doped emitter layer 153 of n-type, a thin antireflection layer 154 covering the emitter layer, highly doped diffusion regions 163 of n+-type (selective emitter), contacts 155 extending through the layer 154 to regions 163, a layer of silicon oxide 156 with openings to the regions 162 of p+-type, and a metallization layer 157 as a rear contact. The surface of the wafer 150a has a pyramidal texture to improve light capture. The base width of the pyramids is from a few micrometers to a few tenths of micrometers. In this arrangement, the junction between the emitter layer 153 and the base region 151a is not planar and has a surface area of a structured pyramidal junction which is 1.7 times larger than the surface of a planar junction. The larger junction surface area results in 1.7 times lager solar cell saturation current thus reducing cell efficiency.
One type of conventional back-contact solar cell is illustrated in FIG. 15B and has a silicon wafer 150b with a base region 151b of n-type conductivity, interdigitated regions 164 of p+-type and regions 165 of n+-type, a front surface field layer 166 of n+-type having a pyramidal textured surface, a thin antireflection layer 154 covering the field layer 166, a layer of silicon oxide 156 with openings to regions 164 and 165, and contacts 176 connected to the regions 164 and 165. In this arrangement, the junction between the front surface field layer 166 and the base region 151b is not planar and has a surface area of a structured pyramidal junction which is 1.7 times larger than the surface of planar junction. The larger junction surface area results in 1.7 times lager solar cell saturation current thus reducing cell efficiency.
FIG. 15C illustrates an example of one type of conventional bifacial solar cell that includes a silicon wafer 150c with a base region 151c of p-type conductivity, a diffusion layer 142 of p+-type (back surface field layer), an emitter layer 153a of n+-type having a pyramid texture surface, a thin antireflection layer 154 covering the emitter layer 153a, front contacts 155 through the antireflection layer 154 to the emitter 153a, and bottom contacts 155 through the antireflection layer 154 to the hack surface field layer 142. In this arrangement, the junction between the emitter layer 153a and the base region 151c is not planar and has a surface area of a structured pyramidal junction which is 1.7 times larger than the surface of planar junction. The larger junction surface area results in 1.7 times lager solar cell saturation current thus reducing cell efficiency.
FIG. 15D illustrates an example of one type of conventional symmetrical bifacial solar cell that includes a silicon wafer 150d with a base region 151d of p-type conductivity, a diffusion layer 142a of p+-type (back surface field layer) having a pyramid texture surface, a thin antireflection layer 154 covering the diffusion layer, an emitter layer 153a of n+-type having a pyramid texture surface, a thin antireflection layer 154 covering the emitter layer, front contacts 155 through the antireflection layer 154 to the emitter 153a, and bottom contacts 155 through the antireflection layer 154 to the back surface field layer 142a. In this arrangement, both junctions between the emitter layer 153a and the base region 151d and between the back surface field layer 142a and the base region 151d are not planar and have surface areas of structured pyramidal junctions which are 1.7 times larger than the surface of planar junction. The larger junction surface areas result in 3.4 times larger solar cell saturation current thus reducing cell efficiency.